( Electrical Eng. Dep. at the Univ. Federal do Rio Grande do Sul – UFRGS )
Topic: Reliability of Nanoscale Semiconductor Devices, focusing on but not limited to Noise and Bias Temperature Instability.
Abstract: Effects that play a major role on the reliability of today digital and analog designs are discussed, as well as effects that are expected to become relevant in future technologies. Modeling techniques to abstract the physical level effects into the design flow are studied.
The main focus of the tutorial will be charge capture and emission by defects (traps) close to the Dielectric-Semiconductor interface is known to be the major source of low-frequency noise in modern MOS devices. It is also known to play a role in Bias Temperature Instability (BTI). The basics mechanisms involved in charge trapping and de-trapping will be presented, including a critical discussion of key parameters such as trapping/de-trapping time constants and the amplitude of the fluctuations induced by single traps. Standard low-frequency noise models used today (e.g. BSIM) do not properly model noise behavior under large signal excitation, and often do not to properly model noise variability. A novel physics based modeling and simulation approach will be presented. It is based on the relevant microscopic quantities that play a role in both low-frequency noise and BTI. The modeling approach is valid at both DC and large signal (AC) biasing, and may be applied to time domain (transient) and frequency domain (AC) analysis. Mutual relation between the different reliability phenomena (low-frequency noise, BTI and random dopant fluctuations – RDF) is also studied. For instance, RDF may exacerbate the impact of BTI and low-frequency noise on circuit performance. Additionally, the LF-noise (and BTI) levels from device-to-device can vary several orders of magnitude in deeply scaled devices, making variability a major concern in advanced MOS technologies. Therefore, to assure proper circuit design in this scenario, it is necessary to identify the fundamental mechanisms responsible for variability in LF-noise and BTI. We introduced a new variability-based analysis, employing the autocorrelation of multiple LF-Noise spectra in terms of parameters such as frequency, bias and temperature. This technique reveals information about the mechanisms responsible for the LF-noise (and BTI) that is difficult to obtain otherwise.
Modeling targeted to time domain analysis of RTN is also discussed. Time domain analysis is relevant for the analysis of digital and mixed-signal circuits. In digital circuits, the RTN chronological statistics, especially trap occupancy switching, has direct impacts on circuit performance and reliability, as degradations like jitter of signals happen when a trap switches state. We study the time-dependent random variability induced by RTN, by providing an analytical model for the threshold voltage jitter produced by RTN. The area scaling of RTN induced jitter and its variability is detailed and discussed, aiming to support circuit designers in transistor sizing towards a more reliable design. The applicability of the model here presented to the evaluation of logic gates and circuits composed by logic gates is studied and demonstrated by the case study of inverters and ring oscillators. The analytical model and sensitivity analysis may be used to avoid the costly Monte Carlo simulations.
The talk is focused on nano scale MOS devices, but novel devices such as Resistive Switching Memory (RRAM/ReRAM) are also addressed.
Summary Background
Gilson Wirth received the B.S.E.E and M.Sc. degrees from the Univ. Federal do Rio Grande do Sul, Brazil, in 1990 and 1994, respectively. In 1999 he received the Dr.-Ing. degree in Electrical Engineering from the University of Dortmund, Dortmund, Germany. He is currently a professor at the Electrical Eng. Dep. at the Univ. Federal do Rio Grande do Sul – UFRGS, where he was the head of graduate and undergraduate courses. He has stablished successful collaborative work with different companies and research groups in Europe, North and South America, and China. He is currently a Distinguished Lecturer of the IEEE Electron Devices Society. He was a Distinguished Lecturer of the IEEE Circuits and Systems Society (term 2010 to 2011).
CV may be found at http://lattes.cnpq.br/1745194055679908.